1. Field of the Invention
The present invention relates to a negative booster circuit employing a switching element having a triple-well structure.
2. Description of the Related Art
In recent years, flash memories, which are a type of non-volatile semiconductor memory devices, require data read and data write using a single power supply voltage or low power supply voltages, for which, therefore, a booster circuit for supplying a positive or negative boosted voltage is required on a chip when each operation is performed. Also, during CMOS processes, a power supply voltage generated by the booster circuit is used to improve characteristics of an analog circuit.
Conventionally, there is a known negative booster circuit employing a triple-well structure switching element (Japanese Unexamined Patent Application Publication No. 2002-237192).
FIG. 10 shows an exemplary conventional negative booster circuit. In FIG. 10, reference symbol 901 indicates a negative booster circuit that receives two-phase clock signals CLK1 and CLK2 and performs a boosting operation to generate an output terminal voltage (negative boosted voltage) Vbb. The negative booster circuit 901 includes a first row of boosting cells 11, 12, 13 and 14 and a second row of boosting cells 21, 22, 23 and 24, where each row includes four stages. CLK1 is input to boosting cells in the odd-numbered stages of the first row and boosting cells in the even-numbered stages of the second row, while CLK2 is input to boosting cells in the even-numbered stages of the first row and boosting cells in the odd-numbered stages of the second row. Reference symbols 15 and 25 indicate backflow preventing circuits for preventing a backflow of the boosted voltage Vbb. Reference symbols M11 to M14 and M21 to M24 indicate charge transfer transistors (N-channel transistors) whose P-wells are connected to the output terminals of boosting cells in the respective next stages for a substrate control and which function as switching devices. Further, reference symbols M15 to M16 and M25 to M26 indicate N-channel transistors in the backflow preventing circuits 15 and 25, and reference symbols C11 to C15 and C21 to C25 indicate booster capacitances.
An operation of the negative booster circuit 901 of FIG. 10 will be briefly described with reference to FIG. 11. For example, attention is paid to the boosting cells 12 and 22 in the second stage.
The two-phase clock signals CLK1 and CLK2 in the negative booster circuit 901 are clocks whose phases are different from each other by 180 degrees.
Initially, at time T1, CLK1 goes to “H” (power supply voltage Vdd) and CLK2 goes to “L” (ground voltage Vss), so that the charge transfer transistor M12 of the boosting cell 12 goes to the non-conductive state, and the output terminal voltage decreases or is negatively boosted. In this case, at the same time, the P-well voltage of the charge transfer transistor M12 also decreases, so that the input/output terminal voltage and the P-well voltage of the charge transfer transistor M12 can be maintained in the reverse-bias state. On the other hand, the output voltage of the boosting cell 22 increases, so that the charge transfer transistor M22 goes to the conductive state, and therefore, charges are transferred from the output terminal to the input terminal of the boosting cell 22. In this case, the input/output terminal voltage and the P-well voltage of the charge transfer transistor M22 simultaneously increase while being maintained in the reverse-bias state, so that charge transfer can be performed while suppressing the substrate bias effect of the charge transfer transistor M22.
Next, at time T2, CLK1 goes to “L” (ground voltage Vss) and CLK2 goes to “H” (power supply voltage Vdd), so that the operations of the boosting cells 12 and 22 can be switched. At time T3, the state goes back to that of time T1, in which a negative boosting operation is repeated.
As described above, according to the negative booster circuit 901 of FIG. 10, the input/output terminal voltage and the P-well voltage of a boosting cell can be controlled while being invariably maintained in the reverse-bias state, so that even when a charge transfer transistor including the input/output terminal (N-diffusion), the P-well and the N-well (triple wells) of a boosting cell is employed, it is possible to prevent a reduction in boosting efficiency due to a parasitic bipolar transistor, thereby further suppressing the substrate bias effect of the charge transfer transistor, so that the charge transfer efficiency during a boosting operation can be improved.
However, in the conventional negative booster circuit 901, for example, the P-well of the charge transfer transistor M12 of the boosting cell 12 is connected to the output terminal of the boosting cell 23. Therefore, a parasitic capacitance formed by the P-well of the charge transfer transistor M12 is charged and discharged by voltage transition widths of the clock signals CLK1 and CLK2 in response to the voltage transitions of the clock signals CLK1 and CLK2. As a result, current consumption disadvantageously increases.
Also, charges supplied by the clock signals CLK1 and CLK2 are used as charges for charging and discharging the P-well of the charge transfer transistor M12. As a result, the boosting efficiency decreases.
Also, since the P-well of the charge transfer transistor M12 is connected to the output terminal of the boosting cell 23, the P-well of the charge transfer transistor M12 needs to be separated from the other charge transfer transistors. As a result, the layout area disadvantageously increases.